Descripción del producto

DISTINCTIVE CHARACTERISTICS
  Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
   Manufactured on 0.*3 µm process technology
— Fully compatible with 0.*2 µm Am*9LV**0B device
   High performance
— Access times as fast as *0 ns
   Ultra low power consumption (typical values at
5MHz)
— **0 nA Automatic Sleep mode current
— **0 nA standby mode current
— 9 mA read current
— *0 mA program/erase current
   Flexible sector architecture
— One *6 Kbyte, two 8 Kbyte, one *2 Kbyte, and
thirty-one *4 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one *6 Kword, and
thirty-one *2 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
     Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
     Top or bottom boot block configurations
available
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
    Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
     Top or bottom boot block configurations
available
 Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
n Minimum 1,**0,**0 write cycle guarantee
per sector
    **-year data retention at **5°C
— Reliable operation for the life of the system
   ackage option
— **-ball FBGA
— **-pin TSOP
— **-pin SO
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
    Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
  Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
    Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion (not available on **-pin SO)
    rase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
 Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data