Descripción del producto

• In-System Programmable PROMs for Configuration of Xilinx FPGAs
• Low-Power Advanced CMOS NOR FLASH Process
• Endurance of *0,**0 Program/Erase Cysels
• Operation over Full Industial Temperature Range ( **0oC to + *5oC )
• IEEE Standard ***9.1/****2 Boundary-Scan (JTAG)Support for Programming, Prototyping,and Testing
• JTAG Command Initiation of Standard FPGA Configuration
• Cascadable for storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG ) I/O Power Supply ( VccJ )
• I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
• Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages

• XCF*1S/XCF*2S/XCF*4S
• 3.3V supply voltage

• Serial FPGA configuration interface ( up to *3 MHZ )
• Avaliable in small-footprint VO*0 and VOG*0 packages.
• XCF*8P/XCF*6P/XCF*2P
• 1.8V supply voltage
• Serial or parallel FPGA configuration interface                                          (up to *3 MHz )
• Available in small-footprint VO*8,VOG*8,FS*8,and FSG*8 packages
• Design revision technology enables storing and accessing multiple design revisions for configuration
• Built-in data decompressor compatible with Xilinx advanced compression technology

• Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to *2 Megabit ( Mbit) densities,these PROMs provide an easy-to-use ,cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3 V SCFxxS and the 1.8V XCFxxP PROM . The XCFxxS version includes *-Mbit,*-Mbit, and *-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes ( Figure 1 ) . The XCFxxP version include **-Mbit,**-Mbit,and *-Mbit PROMs that support Master Serial, Slave Seial, Masster SelectMAP,and Slave SelectMAP FPGA configuaration modes（ Figure 2） . Asummary of the Platform Flash PROM family members and supported features is shouwn in Table 1.